Member of Technical Staff, IC Design
Maxim Integrated
Taipei, Taiwan

Job Description

Maxim Integrated is a highly successful, $2.4 billion company. With offices and manufacturing sites around the world, we design award-winning semiconductors that make the world more integrated.

We also know that it’s our people who make us a great company. So we reward bold thinking, teamwork, personal growth, and community involvement.

Want to make a difference and be challenged every day? Join us at Maxim Integrated. With analog integration, the possibilities are endless.


Maxim is seeking a Mixed-Signal IC Design Engineer to support assigned IC products through the full product life cycle. Assignment is in Mobile Solutions group.

Tasks & Responsibilities

Responsibilities may include, but are not limited to, working with other design group members to :

Create transistor level designs of circuits to meet specifications

Verify designs using transistor-level and behavioral-level simulations

Supervise circuit layout

Perform AMS simulation for top level verification

Model DC-DC switching regulator’s behavior with Simplis or Verilog-A or Verilog-AMS

Read and understand Verilog RTL

Write circuit documentation and test plan

Work with test engineer to firm up test plans and design for testability

Validate circuit performance in the lab

Minimum Qualifications

Minimum qualification :

Master’s degree in Electrical Engineering or related field

3+ years analog / mixed-signal design experience

Solid knowledge of building blocks like bandgaps, operational amplifiers, comparators, relaxation oscillators, PLL, feedback and compensation techniques.

Good writing and verbal communication skills in English

Maxim is an equal opportunity employer and gives consideration for employment to qualified applicants without regard to race, color, religion, sex, national origin, disability or protected veteran status.

Preferred Qualifications

Preferred qualification :

Solid understanding of DC-DC topology such as buck, boost, charge pump and LDO

Proficiency in Cadence design environment and mixed-signal simulation

Familiar with Verilog language is a plus

Familiar with scripting language (Python, C, etc.) is a plus

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