RTL CAD Engineer
Google
New Taipei, Banqiao District, New Taipei City, Taiwan
1天前

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another.

As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people.

We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.

We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Design, develop, and deploy new RTL tools and features
  • Support (improve through profiling) execution of the tools and flows currently used in the RTL design process
  • Design, develop, and support design methodologies, automation scripts, and write documentation
  • Ramp up on an existing front end methodology and support multiple projects
  • Minimum qualifications :

  • Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent practical experience
  • 4 years of RTL relevant experience
  • Scripting and automation experience
  • Preferred qualifications :

  • Experience developing and supporting RTL build and compilation flows, RTL connectivity flows, and IP to SoC handoff / release flows
  • Experience in developing and supporting Design Data Management solutions (git / perforce), and continuous integration flows (Jenkins)
  • Experience with / knowledge of front end design automation / CAD flows like RTL lint, clock domain crossing, IP Release flow
  • Experience with / knowledge of Design Verification technologies like simulation, coverage collection, test planning, compile debug
  • Basic understanding of Verilog or System-Verilog RTL
  • Excellent scripting skills in Perl and / or Python, Makefile, Shell
  • 报告这项工作
    checkmark

    Thank you for reporting this job!

    Your feedback will help us improve the quality of our services.

    申請
    郵箱地址
    通過點擊“持續”,我允許neuvoo同意處理我的數據並向我發送電子郵件提醒,詳見neuvoo的 隱私政策 。我可以隨時撤回我的同意或退訂。
    持續
    申請表