1. Physical implementation of advanced technology chips.
2. Design methodology development and innovation for advanced technology challenges.
3. Be responsible for 16 / 12 / 10 / 7nm chip implementation for internal or customer projects. EDA tool enablement and customer’s support if necessary.
1. MS or above in EE, CS related fields with experience in APR, physical verification, chip implementation, or CAD development.
2. 3+ year working experience in chip physical implementation.
3. Familiar with Synopsys / Cadence APR tools / flows.
4. Can write Tcl / Perl utility program.
5. Experience with TSMC advanced technology is plus.
6. Proven record in production tapeouts.