Design Verification Engineer
MediaTek
ChuPei
3天前

職缺說明

Design Verification Engineer is part of a RD team developing Smart Home device products.

Responsible for

  • Plan and implement verification of complex CPU subsystem or IPs using systemverilog and UVM.
  • Verify designs with systemverilog assertion and formal tools.
  • Develop and optimize verification flow and methodology.
  • Explore and analyze architecture and performance.
  • 職缺需求

    1. Good knowledge of computer architecture and ASIC design flow.

    Experience

    with the verification methodology such as VMM, OVM, or UVM.

    3. Scripting experience using scripting languages like Perl or Tcl.

    4. C / C++ programming is a plus.

    5. SystemC, ESL experience is a plus.

    碩士

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