1. High speed SerDes design and Ethernet IP design : RTL coding / verification / Synthesis
2. Develop ASIC architecture for signal processing and communications algorithms
3. Chip integration and verification
Requirement 1. Better to have chip integration experience
2. Familiar with front-end or back-end implementation flow and related EDA tools
3. Good fundamentals in analog / mixed-signal circuit design.
4. Familiar with switch domain knowledge, and giga-bits Ethernet system knowhow
5. Familiar with Gigabit Ethernet PHY
6. Experience in Ethernet PHY related chip development
7. Experience in high-speed analog front-end, CTLE / DFE, CDR, PLL, equalization
8. Familiar with digital communication, digital signal processing, digital filter, equalizer, timing recovery, and automatic gain control
9. Familiar with data communication standards such as 10G Ethernet, PCIe, SATA, or USB
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