1.SOC architecture design, RTL implementation, and verification.
2.Low power architecture design and power analysis.
3.ASIC development planning and execution.
4.Block and chip level synthesis, timing closure, and formal verification.
5.Chip bring-up and validation support.
1. Familiar with ASIC design flow.
in micro-architecture design and RTL implementation.
3. Experience in low power design and ability of power analysis.
4. Proficient in design and verification tools.
5. Experience in SOC integration (RF, analog).
6. Good understanding of Wi-Fi and Bluetooth specification.
7. Understanding of wireless communication.
8. Experience in chip bring-up and validation.
9. Experience in system verilog is a plus.