You will define APR project plan / schedule with key customer and manage technical execution.
Lead an engineering team to implement chip / block level design from Netlist to GDS, deliver design results based on committed schedule and quality.
Execute the most challenging blocks. Help team members overcome design challenges and train new comers to enhance technical capabilities.
Effectively and consistently communicate overall project status. Identify and resolve conflicts and technical issues quickly and effectively.
MST degree in Electrical Engineering or Computer Science.
20+ years Netlist (or RTL)-GDS hands on physical implementation and project management experiences.
Strong leadership skills, communication skills, interpersonal skills, and partner with different teams within TSMC.
In depth knowledge of major EDA tools / design flows and PPA optimization.
Experience with TSMC N16 or below technology.
Proven record in multi-million gate design production tape-outs.
Ability travel internationally 10-15%.
Fluent in English
Personal Attributes :
o Aggressive in learning and problem-solving.
o Good communication skill and a good team player.
o Strong project ownership and commitment.