1. Micro-architecture and RTL design of AI processor
2. System bus and mobile peripheral designs
1. Architecture design and RTL implementation of AI subsystem
2. AI subsystem integration, design verification and peripheral design
3. AI subsystem performance and low-power analysis
Requirement Requirement one
1. Familiar with processor architecture for massive data processing, such as GPU, DSP.
2 Familiar with Verilog
Familiarity with one or more of following tasks will be a plus
1. Machine Learning, OpenCV or Halide
2. OpenCL or CUDA programming model.
1. Familiar with digital IC design flow. FPGA is a plus.
2. Familiar with SoC integration and design verification flow
3. Experienced in SoC architecture
4. Familiar with DSP / MCU, and bus (ARM bus) system architecture design.
5. Familiar with Perl, C, Verilog and power analysis related tools.
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