What you'll be doing
Lead and execute IC layout of cutting edge, high performance, high speed CMOS integrated circuits in foundry CMOS Finfet process nodes in 5nm and 3nm following industry best practices.
Follow company procedures and practices for IC layout activities.
What we need to see :
Requires 5+ years of experience in high performance analog layout in advanced CMOS process.
Thorough knowledge of industry standard EDA tools for Cadence, Mentor and Synopsys.
Experience with layout of high performance analog blocks such as analog to VCOs, chargepump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, references, etc. is desired.
Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)
Experience with floor planning, block level routing and large macro level assembly.
Knowledge of high performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with sub-micron design in foundry CMOS nodes 5nm and finfet layout rules is preferred.
Experience working in distributed design team is a plus.
Requires self-starter with the ability to define and adhere to a schedule.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status