Digital Design Engineer
MediaTek
HsinChu
4天前

職缺說明

Block Level RTL to GDS implementation.

職缺需求

3 years of hands on experience in physical design (Netlist to GDS)

Experience

d in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.

Experienced in working on advanced process nodes (16nm).

Strong expertise in Physical Verification to debug LVS / DRC issues at block level.

Strong skills with ICC / ICC2 or Encounter.

Understanding of STA and timing constraints.

DCT / DCG based Synthesis.

Experienced in high speed design (>

碩士

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