Block Level RTL to GDS implementation.
3 years of hands on experience in physical design (Netlist to GDS)
d in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
Experienced in working on advanced process nodes (16nm).
Strong expertise in Physical Verification to debug LVS / DRC issues at block level.
Strong skills with ICC / ICC2 or Encounter.
Understanding of STA and timing constraints.
DCT / DCG based Synthesis.
Experienced in high speed design (>