Principal Application Engineer
Cadence Design Systems, Inc.
HSINCHU
2天前

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description :

1. To provide key technical support in digital IC design synthesis products.

2. To demonstrate strong ability and to be hands-on in synthesis / DFT, and low power methodology.

3. To run benchmarks, characterize problems, and support key customer engagements.

4. To work with team, customer and R&D on new methodologies and flow refinement.

5. To have real case exercise and.

Position Requirements :

  • Master with 0-5 years working experience or Bachelor with 3+ years’ experience in IC design. Cadence Genus experience will be a plus.
  • Understanding of synthesis / DFT techniques, constraint and timing analysis is required. Knowledge of power analysis & optimization will be a plus.
  • Experiences in frontent tools. Basic backend concept would be required.
  • Good communication in English and Chinese, good confidence and good self-motivation.
  • Be familiar with shell / perl / tcl etc. script language.
  • We’re doing work that matters. Help us solve what others can’t.

    报告这项工作
    checkmark

    Thank you for reporting this job!

    Your feedback will help us improve the quality of our services.

    申請
    郵箱地址
    通過點擊“持續”,我允許neuvoo同意處理我的數據並向我發送電子郵件提醒,詳見neuvoo的 隱私政策 。我可以隨時撤回我的同意或退訂。
    持續
    申請表