Layout Engineer
台灣積體電路製造股份有限公司
竹科
4天前

Description

1.Develop Standard cell, SRAM, IO, analog IPs

2.Work with TSMC RD to define design rules to meet Area / performance target and provide design rules trade-off on area and performance

3.Find layout solution for std. Cell, SRAM, IO, and analog IP to reduce RDR impact on area

Qualifications

1.Minimum BS degree majoring in EE or Engineering related fields

2.At least 3 years experience in IC layout field

3.Expertise on std. Cell, SRAM and analog layout and familiar with customers usage on those IPs

4.It’s a plus if ability to communicate to customers in fluent English

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