DFT/ATPG technical manager
HsinChu, Taiwan

Job Description

1. Whole chip DFT structure planning and design

2. Negotiate with customer and develop DFT flow

3. Scan / DFT design timing closure

4. DRC debugging and DFT verification

5. Test coverage improvement

6. ATPG MP pattern generation , debug and mass production

Requirement 1. Good DFT fundamental knowledge :

a. Hierarchical scan structure

b. OCC structure

c. Low power scan methodology

d. Test access mechanism (JTAG / P1500 / IJTAG)

e. DRC violation debugging skill

f. SAF / TDF test coverage improvement

g. Pattern porting (TMAX) / pattern retarget (Tessent) skill

2. Familiar with tools

a. DFT : DFT compiler / BSD compiler / TestKompress

b. DC TCL / Tessent Shell

c. Perl / Python for Flow Automation Development

d. TetraMAX / TestKompress ATPG & Diagnosis

e. SPF / Test procedure structure and writing

f. VCS / Debussy for pattern simulation and debugging

3. Experience of RTL / Synthesis ,Timing review / ECO is plus

a. Experience of coworking with physical designer for scan / dft placement guideline is plus

b. Experience of cell-aware atpg / Diagnosis / MCP is plus


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