APR Engineer
台灣積體電路製造股份有限公司
竹科
2天前

Job content :

1.Hands on SOC chip / block implementation from gate level netlist to GDS tape-out.

2.Develop IC design methodology

3.Chip tape-out; Design methodology development

Requirement :

1.Experience in tape-out with multi-million gates count SOC design. 16nm / 10nm / 7nm design experience is a plus.

2.Solid skill sets of Cadence / Synsopsys / Mentor EDA tools.

3.Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM and spice simulations.

4.Experience in CAD methodology and problem solving skill.

5.Familiar with Verilog, Perl / Tcl and C / C++.

6.Good communication in English

7.Master Degree or above

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