Job Description
This position will be involved in the design methodology development with Foundry and EDA in leading-edge process node :
1.Will work extensively with micro-architects to make best-in-class performance / power / area
2.Will drive RTL-to-GDS flow through synthesis and place-and-route to achieve competitive targets for performance / power / area
3.Will work with multi-functional engineering team to implement and validate physical design on the aspects of timing, power, area, reliability, and testability
Requirement This position will require :
1.Proficient programming skills in Python, Tcl , Perl
2.Using synthesis & place-route tools and tape-out experience with optimum recipes
3.Knowledge of timing sign-off fundamentals : signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc. Experience using timing sign-off tools : PrimeTime / Tempus / HSPICE
4.Experience in design margin modeling, including CCS / AOCV / POCV / LVF
5.Familiar with timing sign-off factors : OCV / IR / thermal / Reliability , and spice simulation. Experience in pre-silicon / post-silicon correlation is a plus
6.Working experience in deep submicron N7 / N5 / N3 technologies with device physics knowledge
7.Ability to collaborate effectively with different teams with good communication skill and issue management capability
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