Pr. Digital IC Design Engineer

NXP Semiconductors

Hsinchu

5天前

As a technology leader, NXP is re-imagining how we connect and interact with our advanced portfolio of wireless solutions.

Our in-house experts build on decades of leadership in RF technology to not only guide the ongoing expansion of wireless, but also innovate across the entirety of the wireless spectrum.

From such short range technologies like NFC and Ultra-Wideband, to Wi-Fi 6 and 5G, the NXP team is driving global market adoption of these cutting-edge technologies.

When combined with the processing power of the EdgeVerse platform, NXP is uniquely positioned to enable smart connected devices for IoT, industrial, auto and communication infrastructure applications making lives easier, safer, and more convenient.

Joining the NXP Wireless Connectivity team means you will have unparalleled opportunities to develop the best-in-class products with the latest IEEE standards in advanced processing nodes;

it means you will work with a group of passionate and talented engineers to tackle the most crucial tasks leading the next-generation of innovations including Wi-Fi 7 technologies.

NXP’s Wireless Connectivity team has an open and inclusive work environment that promotes excellence, innovation, collaboration, and integrity.

An expanding business comes with tremendous career opportunities which will challenge and grow your talents. If you are ready to start the next chapter of your career in the wireless area, you don’t want to miss this opportunity to join a world leader in this technology.

NXPs’ Wireless Connectivity team currently have job opening(s) in the following area(s) :

Senior ASIC Design Engineer

Successful candidate for this position would be joining our WiFi digital baseband team in delivering best-in-class WiFi products.

Duties include but not limited to :

Develop micro-architecture of complex DSP blocks

RTL coding, verification and documentation

Area / power optimization and design trade-off analysis

Script development and design automation

Logic synthesis and timing closure

Requirements :

BS or MS / PhD in EE or related discipline

8+ years or more ASIC design experiences

Fluent on RTL coding in Verilog / SystemVerilog

In-depth knowledge on digital logic design, DSP and communication

Experiences in UVM or other verification methodology

Experiences in WiFi or other communication standard a plus

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