What you'll be doing
Post-layout model extraction for project review sign-off.
pre-layout model extraction for DOE.
Work closely w / Package and PCB Design teams to design and ensure link performance meets expectation before tapeout.
Develop novel algorithms & new methodologies to improve SI / PI / EMI modeling efforts.
Work w / Application Engineering teams to support customers w / SI / PI questions.
Drive the next generation display (DP2.0 / HDMI2.1) and USB4.0, and requirements and product definition.
Support signal integrity simulation and analysis for interfaces HBM, LPDDR, PCIE, NVLink, etc.
What we need to see :
MS / PhD, or equivalent experience in EE.
With a minimum 5 years of experience as a SI / PI engineer.
S / Y / Z parameters; discrete signal processing knowledge.
Know how to use ANSYS HFSS / Q3D / SIwave / Designer, Synopsis HSPICE, Cadence PowerSI, and Keysight ADS.
Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus.
Familiarity with high-speed I / O design concepts including clock generation, transmitter & receiver design, and equalization schemes.
Familiarity with transient simulation in tools and understanding of eye diagram methodology.
Exposure to lab measurements including VNA & TDR experience.
Passionate about SI / PI work.
Ways to stand out from the crowd :
Exposure to interface timing budgets and system modeling.
SI analysis flow including frequency and time domain simulation.
PDN analysis flow including model generation and time domain simulation.
PSIJ Analyses involving co-simulation of circuits and PDN models.
On-die PDN modeling; familiarity with ANSYS CSM / REDHAWK.
Experience w / Matlab, Python, VBS, and C.
RF / microwave engineering; EMI / RFI analysis capability.