2020 NCG - Product Engineer
NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer.
As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.
Key Areas of Responsibility
To be the technical owner for productTo drive and deliver reduction in product manufacturing cost as quickly as possible, including integral yield improvement and CoNQ reductionTo drive improvement in product quality, e.
g. adopt ZD best practiceTo drive and continuously improve product manufacturability, including time to yield, R&R improvement, RRR improvement, hold lot prevention, product-process fit, etc.
To provide yield reporting, e.g. feedback to Fab after process improvementTo support root cause finding on customer returnTo support fab / assembly / test centre transfers and volume ramp-upTo feedback on DfX and flag IRS defficiencyTo maintain the industrial producibility report (IPR)
Minimum Skill Set
Every PE to be the technical owner for their productsEvery PE to know IMO tools / reporting, e.g. SRT, BR T, yield / top5 reports, hold reports, MiT / FiT, etc.
Every PE to be able to conduct various yield analysis using DatapowerEvery PE to know at least two baseline diffusion processes and all associated options (know process steps, PCM, fab contacts, etc.
Every PE to be capable to make a matrix batch analysisEvery PE to know assembly processes and advanced packages (specific to their product set)At least one PE per team / MST to be capable to lead a new product ramp-up team or other cross-functional teamAt least one PE per team to be aware of the baseline process technology roadmap and the effects on CQD and ESDEvery PE to be able to perform characterisation on the ATE and / or bench setup unassisted for their responsible products, e.
g. datalog, logic / memory map, Shmoo, mixed signal test characterisationThe test program methods for logic / memory map and mixed test characterisation are to be provided by the test engineerThe product engineer should be capable to tune characterisation and to prepare Shmoo if not available