ASIC Memory System Architect
Taipei, Taiwan

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.

Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure.

You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing.

Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

You will collaborate with hardware and software architects to define future fabric and memory system architecture. You will work on topics that span areas of fabrics, system coherency, MMUs, compression, caches and system memory.

You will develop architectural C-models and analyze performance and power trade-offs. You will work with hardware designers and validation teams to build and test the hardware architectures.

As part of this work, you will participate in the development of technology in fabric, coherency, memory, etc., and filing associated patents.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.

We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.


  • Explore and evaluate the architectural design choices for fabrics, system coherency, MMUs and memory system.
  • Author hardware architectural specification for fabric and memory system IPs.
  • Work with other hardware and software architects to understand and improve the architecture.
  • Develop C-models, simulate and analyze performance and power trade-offs.
  • Work with Hardware design, verification, emulation and validation teams to build and test the hardware architecture.
  • Minimum qualifications :

  • Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.
  • Experience in architecture and / or micro-architecture / design of fabrics, QoS, MMUs.
  • Experience with C or C++.
  • Experience in ASIC architecture performance analysis, tools, and simulators at different abstraction levels (Cycle Accurate, TLM, and / or Functional).
  • Preferred qualifications :

  • PhD in Electrical Engineering or Computer Engineering or related field.
  • 5 years of relevant industry experience.
  • Hands-on experience designing / implementing or validating RTL for Fabric, MMUs, Caches, Memory controllers.
  • Hands-on experience working with 3rd-party vendor solutions.
  • Domain knowledge in one or more of these areas, Coherent interconnects, Caches, memory system.
  • Knowledge of HDL languages such as System Verilog, Verilog.
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