To develop the methodologies of Power Integrity at system level
to achieve product quality from early data-in to signoff stage.
Requirement 1.Master’s degree related to department of Electronic, Electrical Engineering, Computer Science and Information Engineering.
2.Background / knowledge on transmission line theory, IO circuits, high-speed signaling, power noise, impedance profile and electronics packaging
3.Experience in power integrity simulation tools, such as Hspice, HFSS, Sigrity, RedHawk, PowerSI, Agilent ADS
4.Familiarity with chip-power-model (CPM) and equivalent RLC circuit model.
5.Strong organization, communication and problem solving skills
6.Ability to work across organization to achieve goals and thrive in a team-oriented environment
7.Measurement & correlation for power integrity
8.Programming skill, such as perl, tcl, physon
9.It’s better to familiar with IC design flow and validation flow at system level