高速與低功耗GPU實作(P&R), Power / Performance / Area / Schedule改善及FLOW開發
The candidate who fills this position will work closely with GPU hardware designer, IP and flow teams to improve GPU power / performance / area / schedule / yield.
Candidate is responsible for all aspects of physical design and implementation of large GPUs which are targeted at the DTV, smart phone markets.
Responsibilities include GPU hierarchical physical implementation / coordination (floor plan, block assembly, power / clock distribution, timing closure, power, IR, noise analysis and back-end verification).
Also responsible for flow development with focus on improving GPU development schedule, chip cost, chip power, chip performance, yield, and development resources.
Requirement 1.Location : Hsinchu, Taiwan
2.MS (preferred) in EE, with a minimum of 8 years of P&R / Flow experience
3.Prior experience in hierarchical implementing (>
5M Inst) is a must,
4.Strong flow development / enhancement for high-speed / low-power / low-cost / schedule is a plus
5.Prior experience in GPU implementation (Mali, SGX, Tegra, Adreno or other GPU / Graphics / VIDEO IP) is a plus,
6.Strong coding skills in TCL or other industry-standard scripting languages (Perl, C, C++ and make)
7.Understanding of sub-micron silicon issues like noise, cross-talk, IR Drop, and AOCV effects