Technical manager
MediaTek
HsinChu
6天前

職缺說明

1.Familiar with advanced process nodes (Ex. N7 or more advanced )

  • Strong background in process parameters / device characteristic / standard cell performance, power, area index
  • Expertise in Spice-to-Silicon correlation, Smart Phone / CPU product yield improvement task
  • Familiar in Spice simulation and Project Performance, Power, Area analysis / benchmark
  • Understand sign-off flow / criteria, process trend / weakness is plus
  • Good relationship with Fab / Testing House
  • 2.High performance digital circuit (ARM-CPU)

  • At-least 2 3 yrs in ARM-CPU architecture plan / design / implementation in advanced technology (Ex. N16 / N12 / N7 )
  • Special high performance standard cell design (Ex. special adder / flop ) is plus
  • Familiar with digital design kit format (Ex. synopsys liberty), implementation flow / EDA tool (Ex. Synthesis / STA / IR & EM )
  • Good relationship with EDA vendors
  • 3.Working experience : at least 8 10 Yrs

  • Has been project or team manager / leader for 5Yrs+
  • Good communication skill (Ex. English) with cross-function / sites
  • Fab / CPU or Standard Cell Design / Product experience is plus
  • 職缺需求

    1.Familiar with advanced process nodes (Ex. N7 or more advanced )

  • Strong background in process parameters / device characteristic / standard cell performance, power, area index
  • Expertise in Spice-to-Silicon correlation, Smart Phone / CPU product yield improvement task
  • Familiar in Spice simulation and Project Performance, Power, Area analysis / benchmark
  • Understand sign-off flow / criteria, process trend / weakness is plus
  • Good relationship with Fab / Testing House
  • 2.High performance digital circuit (ARM-CPU)

  • At-least 2 3 yrs in ARM-CPU architecture plan / design / implementation in advanced technology (Ex. N16 / N12 / N7 )
  • Special high performance standard cell design (Ex. special adder / flop ) is plus
  • Familiar with digital design kit format (Ex. synopsys liberty), implementation flow / EDA tool (Ex. Synthesis / STA / IR & EM )
  • Good relationship with EDA vendors
  • 3.Working experience : at least 8 10 Yrs

  • Has been project or team manager / leader for 5Yrs+
  • Good communication skill (Ex. English) with cross-function / sites
  • Fab / CPU or Standard Cell Design / Product experience is plus
  • 碩士

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