THE ROLE :
Be part of AMD IO IP team, joining IP design work on host controller IP for next generation of leading-edge super high speed IO, up to 40 Gb / s.
Establishes and maintains AMD high speed IO technological leadership position.
KEY RESPONSIBILITIES :
Takes part in host controller design, based on architectural requirement for next generation IO. Works on RTL code development for IP blocks in Verilog HDL and make sure functional correct and reusable for different product lines.
Deals with complex problems.
Makes technical decisions.
Coaches and mentors junior staff.
PREFERRED EXPERIENCE :
Specialized knowledge of USB 3.1 / 3.2 / 4.0 or Thunderbolt in protocol and link layers is a plus. Specialized knowledge of PCIE or AMBA is a plus.
Expert of Verilog RTL design on large size digital IP.
Fluent English on talking, presentation and writing documents.
Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
Can solve complex, novel and non-recurring problems.
ACADEMIC CREDENTIALS :
MS / BS degree of EE or CS, with profound experience.