1.Collaborate with Analog and Digital designer and define a system / design spec. of Serdes (50G / 100G / 200G PMA, including performance / power / area) that satisfy customer / product requirement and is competitive in the market.
2.Support the validation of IC, including issue analysis, debug and tool development for analysis and debug.
3.Build the pre-IC system level simulation according to the requirement of spec. and evaluate the tradeoff between different architecture.
4.Track the technical evolution and future trends of the Serdes industry, and assist in the direction of product development from the technical view.
Requirement 1.MS degree in EE / CE / CSIE / ME / ECE / PME Control.
2.Familiar with signal processing (Digital Signal Processing) and control theory.
3.Familiar with matlab / Simulink or other system level simulation tools.
4.Better with experience of Serdes (50G / 100G PMA).
5.Better with experience of CDR (Clock Data Recovery) and PLL (Phase Lock Loop).
6.At least have more than 4 years relevant work experiences.
7.Good English speaking and writing capability.