1.SoC Chip Top and Infrastructure integration and physical design
2.Participate in SoC design implementation from logic synthesis to physical implementation stage under the latest technology process
3.Participate in SOC / Sub-System design architecture planning, RTL design rule check, Synthesis, DFT / ATPG, LEC, Timing sign-off, Timing ECO
Requirement 1.Familiar with digital IC design flow and / or Verilog coding
2.Strong problem solving and communication skills
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