1. ARM CPU subsystem platform design & integration
2. CPU post-silicon issue resolving
Requirement 1. RTL design for specific CPU subsystem features
2. RTL sign-off including Spyglass-Lint, Spyglass-DFT, CCD, CCD check, etc.
3. RTL simulation issue resolving
4. Provide design timing constraint (sdc) and power domain information
5. CPU post-silicon issue resolving
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