1. The NOC bus architect is responsible for NOC bus architecture to support MediaTek Smartphone / Tablet.
He or she defines and / or refine SoC top bus architecture, including NOC configuration and topology.
2. This position needs to consider sub-system latency / bandwidth / power requirement and memory subsystem behavior to give best performance / power / cost solution.
The best solution can be judged by simulation or evaluation flow.
3. This position also needs to plan NOC IP spec roadmap to fulfill further NOC requirement and improvement.
4. This position also needs to drive performance simulation and power evaluation methodology.
Requirement More than 8 years of relevant industrial experience in following domains :
1. SOC NOC design and architecture plan.
2. Bus interconnect design and architecture.
3. Bus performance model creation or evaluation.
4. Low power estimation on bus or NOC.
Familiarity with one or more of following tasks is a plus
1. Bus protocol, such as AMBA AXI, CHI
2. Memory subsystem design
3. SystemC modeling
4. Familiar with Verilog design