Physical Design Principal Engineer/Technical Manager
台灣積體電路製造股份有限公司
竹科
5天前

Description

  • Perform the following :
  • o Chip / Block level floorplan

    o Clock tree synthesis

    o RC extraction

    o STA, timing closure

    o IR / EM analysis and fix

    o DRC / LVS / ERC analysis and fix

    o Tape-out sign off

  • Customer on-site support.
  • Qualifications

  • BCH / MST degree in Electrical Engineering or Computer Science.
  • 5-15 years Netlist (or RTL)-GDS physical implementation experience.
  • In depth knowledge of major EDA tools / design flows.
  • Experience with TSMC N16 or below technology.
  • Experience in block level implementation, chip integration and signoff.
  • Experience in Perl / TCL language programming.
  • Proven record in multi-million gate design production tapeouts.
  • Experience in any of the following is a plus :
  • o TSMC N7 and below technology.

    o Low-power implementation methodology.

    o Advanced timing signoff methodology.

    o Independently complete Netlist-GDS P&R, signoff task.

  • Personal Attributes :
  • o Aggressive in learning and problem-solving.

    o Good communication skill and a good team player.

    o Strong project ownership and commitment.

    oSelf-motivated and can work independently.

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