o Chip / Block level floorplan
o Clock tree synthesis
o RC extraction
o STA, timing closure
o IR / EM analysis and fix
o DRC / LVS / ERC analysis and fix
o Tape-out sign off
o TSMC N7 and below technology.
o Low-power implementation methodology.
o Advanced timing signoff methodology.
o Independently complete Netlist-GDS P&R, signoff task.
o Aggressive in learning and problem-solving.
o Good communication skill and a good team player.
o Strong project ownership and commitment.
oSelf-motivated and can work independently.