ASIC Design Verification Engineer
Taipei, Taiwan

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.

Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure.

You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing.

Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As an ASIC Design Verification Engineer, you will be part of a Research and Development team, and your responsibilities will include building verification components, constrained-random testing, end-to-end system testing, and verification closure.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.

We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.


  • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
  • Minimum qualifications :

  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • Experience verifying digital logic at RTL using SystemVerilog for FPGAs and / or ASICs.
  • Experience verifying digital systems using standard IP components / interconnects (microprocessor cores, hierarchical memory subsystems).
  • Experience creating and using verification components and environments in standard verification methodology.
  • Preferred qualifications :

  • Master's or PhD degree in Electrical Engineering or Computer Science.
  • 3 years of relevant work experience.
  • Experience with image processing, computer vision, and / or machine learning applications.
  • Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
  • Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
  • Experience with verification techniques.
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