DDR2 / 3 / 4 IO, LPDDR2 / 3 IO, and Generic IO design and verify.
DDR2 / 3 / 4 and LPDDR23 PHY design and verify.
ESD design and verify.
Master or PhD degree in EE related area is preferred.
Familiar with IP IO / ESD design,DDRn / LPDDRn PHY design,digital design,and GPIO design and verify.
Experience with PLL and DLL design is a plus.
Knowledge of at least one high speed interface standard : DDR2 / 3 / 4 IO, LPDDR2 / 3 IO, and GPIO design and verification.
Must have hands-on experience on analog building blocks : IO cells including driver and receiver design; clock generation and distribution including DLL, phase interpolators, PLL and VCOs.
Understanding of SI / PI issues in Multi-GHz transceiver design.
Please contact Eric Chou with your updated CV and contact information if you're interested in this role. Thank you.