Job content : 1.Hands on SOC chip / block implementation from gate level netlist to GDS tapeout. 2.Develop IC design methodology.
3.Chip tapeout; Design methodology development.
Requirement : 1.Experience in tapeout with multimillion gates count SOC design. 16nm / 10nm / 7nm design experience is a plus.
2.Solid skill sets of Cadence / Synsopsys / Mentor EDA tools. 3.Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM and spice simulations.
4.Experience in CAD methodology and problem solving skill. 5.Familiar with Verilog, Perl / Tcl and C / C++. 6.Good communication in English. 7.Master Degree or above.