Power/PMIC Architect
Google
Taipei, Taiwan
5天前

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another.

As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people.

We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.

We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Evaluate and optimize different power distributions (i.e., voltage rail assignments, regulator assignment).
  • Work with internal and external teams to define architectural details of a Power Management IC (PMIC) and produce detailed documents for the proposed PMIC architecture.
  • Work closely with power architects and produce detailed trade-off analysis of impact of power delivery network (PDN) on different use-case power.
  • Derive and define features for PMIC.
  • Minimum qualifications :

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 5 years of experience in Power Management Integrated Circuits (PMIC) design or power delivery network design.
  • Experience with Application-Specific Integrated Circuit (ASIC) power analysis methodology.
  • Preferred qualifications :

  • Advanced degree in Electronics, Computer Engineering or Computer Science, focusing on computer architecture, performance, and power analysis.
  • Experience with power components, modeling, distribution, and design.
  • Experience in ASIC / PMIC interactions, PMIC architecture, switched-mode power supply, low dropout regulators (LDO), and Integrated regulators.
  • Analog / digital background in LDO, SMPS, load switch. Experience in battery droop mitigation, over-current protection and thermal shutdown.
  • Knowledge of power design techniques (multi threshold voltage / power / voltage domain design, clock / power gating, DVFS / AVS).
  • Knowledge of thermal analysis, resistive thermal models, and heat transfer analysis.
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