Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in implementing CPU by deep submicron N7 / N5 / N3 technologies and be involved in :
Perform CPU development and design integration for CPU subsystem.
Derive and develop Application for Subsystem PPA (Performance, Power, Area) optimization initiatives.
Support SoC in MCU Subsystem from Technical Feasibility Evaluation phase to Post-Silicon debug phase.
Requirement Minimum Qualifications :
Master Degree in Electrical Engineering, Computer Science or Computer Engineering.
At least 3 years of RTL / Integration design or Physical Implementation experience
Familiarity with chip digital design flow, including RTL integration, simulation, STA.
Ability to collaborate effectively with different teams with good communication skill.
Preferred Qualifications :
PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS.
5+ years of RTL / Integration design or Physical Implementation experience
Familiarity with synthesis, power analysis and post silicon debugging
Familiarity with Low power design, including DVFS, dynamic power-off and clock-tree architecture.
Knowledge of timing sign-off fundamentals : signal integrity analysis, cross-talk, IR, and OCV (AOCV, POCV) effects, etc.
Experience using timing sign-off tools : PrimeTime / Tempus
Working experience in deep submicron N7 / N5 / N3 technologies with device physics knowledge
Common knowledge in CPU architecture
Experience with FPGA, DFT or BIST is a PLUS.
Cross-site working experience is a PLUS.