SOC Design Technical Manager/Engineer
MediaTek
HsinChu, Taiwan
4小时前

Job Description

This position will be involved in the design methodology development with Foundry and EDA in leading-edge process node :

1.Will work extensively with micro-architects to make best-in-class performance / power / area

2.Will drive RTL-to-GDS flow through synthesis and place-and-route to achieve competitive targets for performance / power / area

3.Will work with multi-functional engineering team to implement and validate physical design on the aspects of timing, power, area, reliability, and testability

Requirement For Engineer

Minimum requirement :

1.Proficient programming skills either in Python, Perl 2, C / C++, or TCL (at least one)

2.Experienced in following one or multiple domains : Logic synthesis, DFT, place-route tool usage,

DRC pattern inspection, timing signoff tool usage / fundamentals (SI, Xtalk, OCV, etc), power integrity

analysis (IR, EM, PG)

Preferred requirement :

1.Possess data analysis capability, able to figure out patterns and draw conclusions from collected data

For manager / expert’s roles,

Minimum requirement :

1.Tape-out experiences (3+ years) in one or multiple domains : Logic synthesis, DFT, place-route tool usage,

DRC pattern inspection, timing signoff tool usage / fundamentals (SI, Xtalk, OCV, etc), power integrity

analysis (IR, EM, PG)

2.Have recipe development achievements

3.Issue management capability

Preferred requirement :

1.Experience in design margin modeling, including CCS / AOCV / POCV / LVF

2.Familiar with timing sign-off factors : OCV / IR / thermal / Reliability, and spice simulation

3.Plus if experienced in deep submicron N7 / N5 / N3 technologies

4.Big plus if experienced in pre-silicon / post-silicon correlation

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