ESL methodology development
System level modeling
HW / SW system level bottleneck analysis
Requirement 1. RTL design experience
2. CPU architecture knowledge
3. Chip level architecture design or System level C / C++ / SC modeling experience is a plus
4. C / C++ programming is a plus
5. SystemC, TLM2.0 and ESL experience is a plus
6. SW based emualtor (ex : QEMU) or HW based emulator experience is a plus
7. RTOS or driver porting is a plus
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