Design Verification Engineer(DV)

Job Description

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow.

CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan.

It included : integrated simulation / verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation

Need to build up verification plan / bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone / ASIC operating schemes

Need to leverage the latest EDA tool and concept to accomplish the verification plan

Requirement 1. Have a good command of Verilog / System Verilog / C++ / Perl

2. Have good senses of UVM and Formal verification method.

3. ARM Based SOC verification experience is a plus.

4. Chip Level verification experience is a plus.

5. Well Organized, methodical, and detail oriented.

6. Must be a team player and easy to work with


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