Design Verification Engineer(DV)
MediaTek
HsinChu
22小时前

Job Description

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow.

CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan.

It included : integrated simulation / verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation

Need to build up verification plan / bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone / ASIC operating schemes

Need to leverage the latest EDA tool and concept to accomplish the verification plan

Requirement 1. Have a good command of Verilog / System Verilog / C++ / Perl

2. Have good senses of UVM and Formal verification method.

3. ARM Based SOC verification experience is a plus.

4. Chip Level verification experience is a plus.

5. Well Organized, methodical, and detail oriented.

6. Must be a team player and easy to work with

报告这项工作
checkmark

Thank you for reporting this job!

Your feedback will help us improve the quality of our services.

申請
郵箱地址
通過點擊“持續”,我允許neuvoo同意處理我的數據並向我發送電子郵件提醒,詳見neuvoo的 隱私政策 。我可以隨時撤回我的同意或退訂。
持續
申請表