Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves.
Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure.
You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing.
Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.
We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Define power management details for an ASIC to deliver maximum performance under power and thermal constraints. Define power goals, identify power scenarios, and track IP power.
Establish and drive low power states and corresponding product power goals.
Perform algorithm development, modeling and analysis of power management approaches.
Identify power optimization techniques applicable at different design levels.
Produce detailed documents for the proposed implementation or power management block. Drive trade-off analysis for engineering reviews and product roadmap decisions.
Minimum qualifications :
Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience in power management or power design / methodology.
Experience with ASIC power analysis methodology.
Preferred qualifications :
MS / PhD degree in Electronics or Computer Engineering / Science, with an emphasis on computer architecture, performance, power analysis.
Experience with power modeling, power distribution networks.
Experience with power optimization techniques (multi Vth / power / voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
Experience in droop detection / mitigation / adaptive clock distribution / aging and process monitors.
Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system, such as thermal or peak power mitigation.
Familiar with PMIC, SMPS, LDO and power delivery.