Job Description

1. 10G / 5G / 2.5G Ethernet MAC / BASET PHY design : RTL coding / verification / Synthesis

2. Develop ASIC architecture for signal processing and communications algorithms

3. Chip integration and verification

Requirement 1. Better to have IP development and integration experience

2. Familiar with front-end or back-end implementation flow and related EDA tools

3. Good fundamentals in analog / mixed-signal circuit design.

4. Familiar with switch domain knowledge, and giga-bits Ethernet system knowhow

5. Familiar with Gigabit Ethernet PHY

6. Experience in Ethernet PHY related chip development

7. Familiar with data communication standards such as 10G Ethernet, MACSEC, TSN, 2.5GBASET PHY