Job description Responsible to develop and deliver Foundry PDK’s for various nodes. The PDKs will include all device which will support symbol / spectre / auCdl / auLvs / layout / ivpcell views and will have to align to Foundry PDK style / installation following Foundry development methodology.
Each of these PDK will have to tested and qualified as per Foundry guidelines. Working closely (developing good relation) with the Cadence Services PDK creation team, understanding their process and methodologies related to PDK development Familiarity with the breadth of PDK development practices across multiple foundries / customers Deployment of reference flow / methodology for validation / coverage / performance for PDKs and its maintenance Responding to information requests and inquiries from customers related to PDK and Cadence Tools methodology Education and Experience Bachelors in Electrical / Electronic?
Engineering + 6-7 years of related experience, or Masters + 4-5 years of related experience Technical Skills Good understanding of PDKs and CAD driven flows, Work experience of developing PDK device library components and definitions such as SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation / netlisting, Knowledge of deep sub-micron CMOS processes, device physics and layout design, Experience in scripting languages - Cadence SKILL language, UNIX Shell, Perl, Experience with Cadence Virtuoso layout tools, ADE, Spectre and physical verification tools (Assura / PVS) for DRC, LVS and parasitic extraction, and, Familiarity with development of test cases, its infrastructure, statistical analysis coverage, performance and automation.
ability to create and deliver presentations tailored to the audience needs.