In this position, you will be responsible for all the DFT related matters in Microchip’s Wireless SoC Development. Your scope of work includes but not limited to :
Perform DFT logic insertion and stitching into RTL code or netlists using EDA / CAD tools for ATPG scan (internal / compressed stuck-
at and at-speed scan), Memory BIST, and Boundary Scan.
Work closely with front-end team to ensure the logic structures permit and are suitable for DFT insertion.
Work closely with front-end and back end implementation team to ensure that DFT implementation does not impact the functionality and timing of the chip
Develop timing constraint (SDC) files for DFT modes and corners
Perform STA and drive for timing closure in DFT modes and corners
Develop DFT test benches
Perform gate-level simulation to ensure the post-layout design passed the DFT test benches
Prepare and Debug DFT test patterns for production team
Develop DFT methodology to improve runtime and design testability
Perform DFT sign-off checklist and reviews
SKILL REQUIREMENTS :
Expertise in Design for Test, ATPG, MBIST, and JTAG preferably with Mentor Graphics / Tessent tools.
Familiarity with Synthesis, Formal Verification, and Static Timing Analysis preferably with Synopsys tools.
Familiarity with Verilog, Verilog simulation, and debug.
Familiarity with Tcl, Perl, Python, and Shell scripting.
Familiarity with low-power implementation techniques (UPF).
Familiarity with early-stage optimization checking (LINT, CDC, constraint analysis) to reduce design cycle time preferably with Atrenta SpyGlass tools.
Familiarity with MIPS or ARM cores.
Good communication and team work skills.
MINIMUM EXPERIENCE :
BS / MS in Electrical / Electronics / Computing Engineering required. Previous experience in DFT is a must. Advanced degree in an engineering discipline is a plus.
5+ years of experience in SoC IC design preferably in wireless (802.11 or Bluetooth) products.
Strong understanding of digital implementation tools and flow.
Experience with advance technology nodes (65nm and below).
Experience with UPF-based low power design.
Experience with advance DFT techniques (at-speed-test / compression scan).
Familiar with back-end implementation (P&R) tools and flow.
English Language proficiency highly desirable.
We are looking for candidates who are self-motivators, energetic, and team players. Candidates will need to do some light travel to support the global wireless team.