Job Description and Requirements
R&D Manager I NVM Design Manager
The ideal candidate will be a team lead of a next generation advanced NVM and have the opportunities to participate in IP generation.
The candidate must be a team player with good written and verbal communication skills, and is self-motivated, detail oriented, and able to work with cross-functional teams.
Contribute in all parts of advance memory development flow, starting at design spec.
Tapeout NVM TestChip and IP design in multiple technologies and foundries
Lead NVM team from project start to testchip tapoeut
Work with Product Engineer to perform silicon verification, test and debug to analyze the IP on silicon
Post layout extraction & simulation, testing in conjunction with silicon validation.
Working with layout designers
Skills and Experience Required
10+ years of industry experience as a memory or non-volatile memory circuit designer
Familiar with TestChip tapeout flow
Strong fundamentals of transistor level CMOS analog design
Familiar with circuit simulation tools (HSIM, HSPICE, etc.) is required
Must have prior experience with Industry standard design and layout tool (Custom Complier and ICV is a plus)
Hands-on experience on sense-amplifier, charge pump, high voltage regulator, and bandgap reference design
Experience with statistical design methodology (generating and analyzing Monte-Carlo results)
Hands-on experience of Si debugging (FIB, micro-probing, post layout RC extraction, etc.)
Experience with Low power design and power management circuitry
Experience with FinFET design is a plus