SOC Physical Design Engineer-新竹
Faraday Technology Corporation
新竹
23天前

1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.

2. Responsible for physical verification including DRC, LVS and ESD checking.

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